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hm62v256 series 32,768-word 8-bit low voltage operation cmos static ram ade-203-136e (z) rev. 5.0 jun. 19, 1995 features low voltage operation sram operating supply voltage: 2.7 v to 3.6 v 0.8 m m hi-cmos process high speed access time: 70/85/100 ns (max) low power standby: 0.15 m w (typ) completely static memory no clock or timing strobe required directly lvttl compatible: all inputs and outputs ordering information type no. access time package hm62v256lfp-10t 100 ns 450 mil 280 pin plastic sop (fp-28da) hm62v256lfp-7slt hm62v256lfp-10slt 70 ns 100 ns HM62V256LFP-8ULT 85 ns hm62v256lt-10 100 ns 8 mm 14 mm 32 pin tsop (normal type) (tfp-32da) hm62v256lt-8sl 85 ns hm62v256ltm-10 100 ns 8 mm 13.4 mm 28-pin tsop (normal type) (tfp-28da) hm62v256ltm-7sl hm62v256ltm-10sl 70 ns 100 ns hm62v256ltm-8ul 85 ns
hm62v256 series 2 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ss a10 cs nc i/o7 i/o6 i/o5 i/o4 i/o3 v i/o2 i/o1 i/o0 a0 nc a1 a2 oe a11 nc a9 a8 a13 we v a14 a12 a7 a6 a5 nc a4 a3 cc 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ss a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 v i/o2 i/o1 i/o0 a0 a1 a2 oe a11 a9 a8 a13 we v a14 a12 a7 a6 a5 a4 a3 cc hm62w256lfp series hm62w256lt series hm62w256ltm series (top view) (top view) (top view)
hm62v256 series 3 pin description pin name function a0 to a14 address inputs i/o0 to i/o7 data input/output cs chip select we write enable oe output enable nc no connection v cc power supply v ss ground
hm62v256 series 4 block diagram ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a12 a5 a3 (msb) (lsb) a14 a13 a4 a8 a7 a6 i/o0 i/o7 cs we oe a2 a1 a0 a10 a11 (lsb) (msb) a9 v v cc ss row decoder memory matrix 512 512 column i/o column decoder input data control timing pulse generator read/write control
hm62v256 series 5 function table we cs oe mode v cc current i/o pin ref. cycle x h x not selected i sb , i sb1 high-z h l h output disable i cc high-z h l l read i cc dout read cycle (1)?3) l l h write i cc din write cycle (1) l l l write i cc din write cycle (2) note: x: h or l absolute maximum ratings parameter symbol value unit power supply voltage *1 v cc ?.5 to 4.6 v terminal voltage *1 v t ?.5* 2 to v cc +0.5 *3 v power dissipation p t 1.0 w operating temperature topr 0 to + 70 c storage temperature tstg ?5 to +125 c storage temperature under bias tbias ?0 to +85 c notes: 1. relative to v ss 2. v t min: ?.0 v for pulse half-width 50 ns 3. maximum voltage is 4.6v recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit supply voltage v cc 2.7 3.0 3.6 v v ss 000v input high(logic 1) voltage v ih 0.7v cc ? cc +0.3 v input low(logic 0) voltage v il ?.3 *1 0.2v cc v note: 1. v t min: ?.0 v for pulse half-width 50 ns
hm62v256 series 6 dc characteristics (ta = 0 to +70 c, v cc = 2.7 v to 3.6v, v ss = 0 v) parameter symbol min typ *1 max unit test conditions input leakage current |i li | 1 m av ss vin v cc output leakage current |i lo | 1 m a cs = v ih or oe = v ih or we = v il , v ss v i/o v cc operating power supply current (dc) i ccdc1 15 ma cs = v il , others = v ih / v il i i/o = 0 ma i ccdc2 10 ma cs 0.2 v, v ih 3 v cc ?0.2 v, v il 0.2 v, i i/o = 0 ma average operating power supply current hm62v256-7 i ccac1 30 ma min cycle, duty = 100 %, i i/o = 0 ma cs = v il , others = v ih / v il hm62v256-8 i ccac1 27 hm62v256-10 i ccac1 24 i ccac2 15 ma cycle time 3 1 m s, duty = 100% i i/o = 0 ma, cs 0.2 v, v ih 3 v cc ?0.2 v, v il 0.2 v standby power supply current i sb 0.1 1 ma cs = v ih i sb1 0.05 50 m a vin 3 0 v, cs 3 v cc ?0.2 v, 0.05 10 *2 0.05 4 *3 output low voltage v ol 0.2 v i ol = 20 m a output high voltage v oh v cc 0.2 v i oh = ?0 m a notes: 1. typical values are at v cc = 3.0 v, ta = +25 c and not guaranteed. 2. this characteristic is guaranteed only for l-sl version. 3. this characteristic is guaranteed only for l-ul version. capacitance (ta = 25 c, f = 1.0 mhz) parameter symbol min typ max unit test conditions input capacitance *1 cin 5 pf vin = 0 v input/output capacitance *1 c i/o 8 pfv i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
hm62v256 series 7 ac characteristics (ta = 0 to +70 c, v cc = 2.7 v to 3.6 v, unless otherwise noted.) test conditions input pulse levels: 0.4 v to 2.4 v input rise and fall time: 5 ns input and output timing reference level: 1.4 v dout 500 w 1.4 v 50 pf* output load (including scope & jig) read cycle hm62v256 -7 -8 -10 parameter symbol min max min max min max unit notes read cycle time t rc 70 85 100 ns address access time t aa 70 85 100 ns chip select access time t acs 70 85 100 ns output enable to output valid t oe 35 45 50ns chip selection to output in low-z t clz 10?010?s2 output enable to output in low-z t olz 555 ns2 chip deselection to output in high-z t chz 0 25 0 30 0 35 ns 1, 2 output disable to output in high-z t ohz 0 25 0 30 0 35 ns 1, 2 output hold from address change t oh 10?010?s notes: 1. t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested.
hm62v256 series 8 read timing waveform (1) ( we = v ih ) t t t t t rc aa acs oe olz t oh t ohz t chz valid data address cs oe dout high impedance valid address read timing waveform (2) ( we = v ih , cs = v il , oe = v il ) address t t rc t oh t oh valid data dout aa valid address read timing waveform (3) ( we = v ih , oe = v il ) *1 t acs dout note: 1. address must be valid prior to or simultaneously with cs going low. valid data t chz cs t clz high impedance
hm62v256 series 9 write cycle hm62v256 -7 -8 -10 parameter symbol min max min max min max unit notes write cycle time t wc 70 85 100 ns chip selection to end of write t cw 50?580?s4 address setup time t as 000 ns5 address valid to end of write t aw 50?580?s write pulse width t wp 45 55 60 ns 3, 8 write recovery time t wr 000 ns6 write to output in high-z t whz 0 25 0 30 0 35 ns 1, 2, 7 data to write time overlap t dw 30?540?s data hold from write time t dh 000 ns output active from end of write t ow 10?010?s2 output disable to output in high-z t ohz 0 25 0 30 0 35 ns 1, 2, 7 notes: 1. t ohz and t whz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. a write occurs during the overlap (t wp ) of a low cs and a low we . a write begins at the later transition of cs going low or we going low. a write ends at the earlier transition of cs going high or we going high. t wp is measured from the beginning of write to the end of write. 4. t cw is measured from cs going low to the end of write. 5. t as is measured from the address valid to the beginning of write. 6. t wr is measured from the earlier of we or cs going high to the end of write cycle. 7. during this period, i/o pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. in the write cycle with oe low fixed, t wp must satisfy the following equation to avoid a problem of data bus contention, t wp 3 t whz max + t dw min.
hm62v256 series 10 write timing waveform (1) ( oe clock) t wc t cw t wp t as t ohz t dw t dh t aw t wr *1 address oe cs we dout din valid data valid address high impedance high impedance notes: 1. if cs goes low simultaneously with we going low or after we going low, the outputs remain in the high impedance state.
hm62v256 series 11 write timing waveform (2) ( oe low fixed) address we dout din t wc t cw t wp t whz t dw t dh *1 t as cs t aw *2 *4 *3 t oh t ow t wr valid data valid address high impedance notes: 1. if cs goes low simultaneously with we going low or after we going low, the outputs remain in the high impedance state. 2. dout is the same phase of the write data of this write cycle. 3. dout is the read data of next address. 4. if cs is low during this period, i/o pins are in the output state. therefore, the input signals of the opposite phase to the output must not be applied to them.
hm62v256 series 12 low v cc data retention characteristics (ta = 0 to +70 c) parameter symbol min typ* 1 max unit test conditions *6 v cc for data retention v dr 2.0 3.6 v cs 3 v cc ?0.2 v, vin 3 0 v data retention current i ccdr 0.05 27 *2 m av cc = 2.7 v, vin 3 0 v cs 3 v cc ?0.2 v 0.05 7 *3 0.05 2 *4 chip deselect to data retention time t cdr 0 ns see retention waveform operation recovery time t r t rc *5 ns notes: 1. typical values are at v cc = 2.7 v, ta = 25 c and not guaranteed. 2. 9 m a max at ta = 0 to 40 c. 3. this characteristics guaranteed for only l-sl version. 2.0 m a max at ta = 0 to 40 c. 4. this characteristics guaranteed for only l-ul version. 0.4 m a max at ta = 0 to 40 c. 5. t rc = read cycle time. 6. cs controls address buffer, we buffer, oe buffer, and din buffer. if cs controls data retention mode, other input levels (address, we , oe , i/o) can be in the high impedance state. low v cc data retention timing waveform cc v 2.7 v 0.7 v 0 v cs t cdr t r cs v ?0.2 v cc > dr v data retention mode cc
hm62v256 series 13 package dimensions hm62v256lfp series (fp-28da) unit: mm + 0.08 ?0.07 0.17 0.20 ?0.10 3.00 max 1.27 ?0.10 0.40 + 0.10 ?0.05 8.40 18.00 18.75 max 1.27 max 28 15 1 14 11.80 ?0.30 0 ?10 1.00 ?0.20 1.70 hm62v256lt series (tfp-32da) unit: mm 0.08 m 0.50 8.00 8.20 max 0.20 ?0.10 14.00 ?0.20 1.20 max 12.40 32 116 17 0.17 ?0.05 0.13 ?0.05 0 ?5 0.45 max 0.10 0.50 ?0.10 0.80
hm62v256 series 14 hm62v256ltm series (tfp-28da) unit: mm 0.10 m 0.55 8.00 0.20 13.4 ?0.3 0.15 0.05 1.2 max 11.80 5?max 21 22 7 8 8.15 max +0.10 ?.05 +0.05 ?.02 0.10 +0.10 ?.05 0.50 ?0.10 0.80 0.63 max

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